1. Field of the Invention
This invention relates to the field of computer system architecture. More particularly, this invention relates to mechanisms for controlling bus bandwidth utilization for a shared resource.
2. Background
In a computer system, peripheral components, such as disk drive controllers, network controllers, and graphics controllers, may be coupled to peripheral component buses separate from a host, or CPU bus. There are several reasons a system might employ peripheral component buses. For example, it may be desirable to isolate slower speed devices from higher bandwidth buses and peripherals. Also, an intelligent peripheral component may have a local peripheral component bus. Moreover, the system may have more peripheral components than can be reliably placed on the host bus, due to electrical loading effects.
In such a system, a host bridge circuit enables communication between the peripheral component bus and a host bus. The host bridge circuit can also enable access to a shared resource from both buses. In the case of a shared main memory resource comprised of DRAM, the host bridge circuit receives DRAM access requests from peripheral components coupled to the peripheral component bus, and in turn performs the requested accesses of DRAM.
However, highly active peripheral components coupled to the peripheral component bus can adversely impact host bus to DRAM performance. In particular, peripheral components capable of extended burst transfers over the peripheral component bus can effectively lock out DRAM accesses from the host bus. The effect of peripheral component bandwidth on host bus performance varies with system configuration. The variables include the number of peripheral components coupled to the peripheral bus, the types of peripheral components coupled to the peripheral component bus, the software applications run on the system, and the demands the CPU has on DRAM (i.e. execution bandwidth load).
Past host bridge circuits simply buffered data for the shared resource without regard for system configuration, and without hardware or software mechanisms to balance loading of the shared resource. With past host bridge circuits, the more peripherals accessing the shared resource, and the higher the bandwidth of the peripherals, the greater the adverse impact on host bus performance.
To minimize the adverse effect on host to shared resource utilization caused by very active components on a peripheral component bus competing for the shared resource, it is desirable to provide a mechanism for the system I/O software to tune the dynamics of bandwidth utilization for the peripheral components. Such a mechanism would enable the system I/O software to conduct empirical tests to determine the proper balance between peripheral component bus performance and host bus performance when accessing the shared resource.
As will be described, the present method and apparatus provides a mechanism that enables system I/O software to dynamically tune peripheral component bandwidth utilization. The present method and apparatus enables the system I/O software to establish the maximum amount of data allowed for a given burst access of a shared resource by the peripheral components.